The present invention relates to a digital modulator with several amplitude levels and d.c. component compensation. It is used in telecommunications and particularly digital transmission.
A known digital modulator is shown in FIG. 1 and comprises:
an input E with two accesses receiving the digital data d.sub.0, d.sub.1,
code conversion circuit 10 with two inputs 10/1, 10/2 connected to two accesses and with two outputs 10/3, 10/4 supplying code converter digital data a.sub.0, a.sub.1,
carrier generator 12 having a phase control input 12/1, connected in the present case to input 10/2 and with an output 12/2 supplying a signal, whose phase is equal to 0 or .pi., as a function of the value of d.sub.1,
a digital-analog converter having two stages, the first being formed by two logic gates 14, 16 (in the present case of the NOR type) having two inputs, respectively 14/1, 14/2 and 16/1, 16/2 and an output, respectively 14/3, 16/3, inputs 14/1, 16/1 being connected to the outputs 10/3, 10/4 of the code conversion circuit 10, and inputs 14/2, 16/2 to the output 12/2 of the generator, the second stage being formed by two transistors 18, 20, whose bases are connected to the outputs 14/3, 16/3 of the logic gates, the collectors to a first supply line 22 raised to a potential Vcc and the emitters to a second supply line 24 raised to a potential V.sub.EE across two load resistors 26, 28 of value 3R and R,
an output S constituted by a matched load line connected to the first line 22.
This circuit functions in the following way. The carrier generator 12 supplies a square-wave signal, whose frequency is the carrier frequency and whose phase is 0 or .pi., as a function of whether d.sub.1 is equal to 1 or 0.
The code conversion circuit 10 supplies data a.sub.0, a.sub.1 defined on the basis of data d.sub.0, d.sub.1, in accordance with the following table, which also gives the phase of the square-wave signal:
______________________________________ d.sub.1 d.sub.0 a.sub.1 a.sub.0 Phase Level ______________________________________ 1 1 0 1 0 +3 1 0 1 0 0 +1 0 1 1 0 .pi. -1 0 0 0 1 .pi. -3 ______________________________________
The load resistor 26 of transistor 18 controlled via a.sub.0 has a 3 times higher value than the load resistor 28 of transistor 20 controlled via a.sub.1 (i.e. respectively 3R and R). The two possible amplitude levels at output S are consequently in a ratio of 3. These levels are indicated in relative values in the final column of the preceding table (symbol+corresponding to phase 0 and symbol 0 to phase .pi.).
FIG. 2 represents the signal obtained at the output of the modulator (at the bottom) as a function of the data values (at the top).
The circuit described hereinbefore is known. The digital-analog conversion part is described in French Pat. publication No. 2454726 corresponding to European Patent Publication No. 80/02348 and the carrier wave modulation part in U.S. Pat. No. 4,433,310.
Such a modulator has the disadvantage of supplying a signal having a d.c. component, because the two voltages forming it do not have the same mean value. Thus, as is clearly apparent from FIG. 2 for d.sub.1 =d.sub.0, the mean value of the voltage is v/2, if v designates the maximum amplitude, whereas for d.sub.1 .noteq.d.sub.0, the mean value is equal to v-v/6=(5v/6).
Thus, apart from the component around the carrier frequency, the spectrum of the modulated signal also has a low frequency component.
These two components of the spectrum are sufficiently spaced apart, when the modulation rate is low compared with the carrier frequency to enable a filter, formed by a simple connecting capacitor, to eliminate the low frequency part of the spectrum without modifying the useful part around the carrier frequency. However, when the modulation rate is no longer negligible compared with the carrier frequency, the low frequency part of the spectrum and the useful part around the carrier frequency overlap. It is then no longer possible to eliminate the low frequency part without distorting the useful part.